Research Areas
Computer Architecture, Computer Security
Research Overview
My research is in computer architecture and computer security, and
how computer architecture can be used to improve computer security.
I have been professing the hardware-up method for securing
computer systems for awhile now. While security is a full-system property,
and both software and hardware have to be secure for a system to be
secure, I believe that the most practical and principled way to achieve
full-system security is to secure the hardware first against attacks,
and then systematically harden each layer in the systems stack as we
move up the stack through the microarchitecture, ISA interface, system
software and application software. This method allows us to avoid security
blind spots in the lower levels when designing security at higher levels
in the systems stack.
Following this approach, we have invented methods for detecting and mitigating backdoors/trojans
embedded in the hardware during its design or manufacturing,
measuring and mitigating security vulnerabilities due to microarchitectural side channels, and developed
architecture support for mitigating common
software problems such as memory safety and malware attacks. We have built
several end-to-end FPGA based demonstrations
including our Polyglot system for preventing code injection and code
reuse attacks, and the Silicon AV malware detection system that uses
on-chip performance counters.
Most recently we have been studying mechanism design for improving
security.
A common denominator among computer architecture and computer
security is the need to understand program
behavior. What began as a quest to automatically discover
special-purpose functional units (accelerators) has resulted in
large number of works from methods to precisely measure execution
times, to techniques for identifying similar code sequences in large
code bases, to techniques for detecting malware at runtime, and the
discovery of power law behaviors in programs!
We have also worked on improving the energy-efficiency and
performance of post-Moore's-Law computers.
We devised an analog accelerator that can provide performance benefits
beyond digital accelerators today by side-stepping the 'digital
tax' in terms of clock and value discretization, showed how they
can be integrated into systems. We built some ASIC chips, and ran robotics and scientific
applications, and showed that certain types of workloads run faster
and consume less energy compared to state-of-the-art GPUs.
Finally, a long time ago, when I was a graduate student at
UT-Austin, I contributed to the design,
implementation, validation and bring-up of the distributed TRIPS
processor, and also devised a follow-on composable microarchitecture.
Recognition
Thanks to my excellent students and collaborators!
- Distinguished Paper Award, Usenix Security 2017
- IEEE Micro Top Picks Selection: 2004, 2013, 2017, 2023
- IEEE Micro Top Picks Honorable Mention: 2018, 2020
- Best Student Paper Award, ACM Computer and Communications Security 2013
- Distinguished Paper Award, ACM International Conference on Program Comprehension 2016
- Best of Computer Architecture Letters, 2016
Ongoing Projects
Mechanism Design for
Security (1,2,3 4), Improving Memory Safety, Co-design of Reliability and Security features, and Cloud Security.
Publications
Hardware Security
-
Trustworthy Hardware from Untrustworthy Components
CACM, Sept 2015
(Article, Video)
-
Silencing Hardware Backdoors
IEEE Security and Privacy 2011 (Oakland 11)
(pdf)
-
FANCI: Identification of Stealthy Malicious Logic Using Boolean Functional Analysis
CCS 2013 Best Student Paper Award
(pdf)
-
A Red Team/Blue Team Assessment of Functional Analysis Methods for
Malicious Circuit Identification
DAC 2014
(pdf)
-
Security Implications of Third-Party Accelerators
Computer Architecture Letters 2015
(pdf)
-
Practical Lightweight Secure Inclusion of Third-Party Intellectual Property
(IEEE Design and Test)
(
pdf)
-
Tamper Evident Microprocessors
IEEE Security and Privacy 2010 (Oakland 10)
(pdf)
Microarchitectural Side Channels
-
CLKSCREW: Exposing the Perils of Security Oblivious Energy Management
Usenix Security 2017 Usenix Security Distinguished Paper Award and IEEE Micro Top Picks Selection
(pdf, Black Hat Talk Video)
-
Side-Channel Vulnerability Factor: A Metric for Measuring Information Leakage
ISCA 12, IEEE Micro Top Picks Selection
(pdf, software)
-
Side-Channel Vulnerability Factor: SVF vs CSV
Workshop on Duplicating, Deconstructing and Debunking
(pdf)
- TimeWarp: Rethinking Timekeeping and Performance Monitoring Mechanisms
to Mitigate Side-Channel Attacks
ISCA 12
(pdf)
- The Spy in the Sandbox: Practical Cache Attacks in Javascript and
their Implications
CCS 2015
(pdf)
Architectural Support for Memory Safety
-
ZeRO: Zero-Overhead Resilient Operation Under Pointer Integrity Attacks
ISCA 2020
(pdf)
-
No-FAT: Architectural Support for Low Overhead Memory Safety Checks
ISCA 2020
(pdf)
- EPI: Efficient Pointer Integrity For Securing Embedded Systems
SEED 2021
(pdf)
- Practical Byte-Granular Memory Blacklisting using Califorms
MICRO 2019
(pdf, arxiv)
IEEE Micro Top Picks Honorable Mention
-
Practical Memory Safety with REST
ISCA 2018
(pdf)
Exploit Detection and Mitigation using Machine
Learning
-
Blacklist Core: Machine-Learning Based Dynamic Operating-Performance-Point Blacklisting for Mitigating Power-Management Security Attacks
ISLPED 2018
(pdf)
-
A Silicon Anti-virus Engine
Hot Chips 2015 Best Poster Award
(Poster, Demo)
-
Unsupervised Anomaly-based Malware Detection using Hardware Features
RAID 2014
(pdf)
-
On the Feasibility of Online Malware Detection with Performance Counters
ISCA 13
(pdf)
Architecture Support for Isolation
-
Heterogeneous Isolated Execution for Commodity GPUs
ASPLOS 2019
(pdf)
-
Reviving Instruction Set Randomization
HOST 2017
(pdf)
- WHISK: An Uncore Architecture for Dynamic Information Flow Tracking in
Heterogeneous Embedded SoCs
CODES+ISSS 2013
(pdf)
Software Only Approaches for Security
-
YOLO: Frequently Resetting Cyber-Physical Systems for Security
SPIE 2019
(pdf,
arxiv,
demo)
-
Heisenbyte: Thwarting Memory Disclosure Attacks using Destructive Code Reads
CCS 2015
(pdf)
-
Concurrency Attacks
HotPar 12
(web)
- Crylogger: Detecting Crypto Misuses for Android and Java Apps
Dynamically, IEEE SP 2021
(pdf)
Next Gen Accelerators and Architectures
-
Hybrid Analog-Digital Solution of Nonlinear Partial Differential Equations
Micro 2017, IEEE Micro Top Picks Honorable Mention
(pdf)
-
An Analog Acceleator for Linear Algebra
ISCA 2016, IEEE Micro Top Picks Selection
(pdf)
-
Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time
JSSC Vol 51(7), ESSCIRC 2015
(Conference, Journal)
-
Increasing Reconfigurability with Memristive Interconnects
ICCD 2015
( pdf )
- A Case for Hybrid Discrete-Continuous Architectures
Computer Architecture Letters 2011
(pdf)
Program Characterization
-
Why Do Programs Have Heavy Tails?
IISWC 2017, Computer Architecture Letters 2016
(pdf, pdf)
-
Robobench: Towards Sustainable Robotics System Benchmarking
ICRA 2016
(pdf)
-
Rapid Identification of Architectural Bottlenecks via Precise Event Counting
ISCA 11
(pdf,software)
-
Code Relatives: Detecting Similarly Behaving Software
FSE 2016
(pdf)
-
Identifying Functionally Similar Code in Complex Codebases
ICPC 2016 Distinguished Paper Award
(pdf)
-
Approximate Graph Clustering for Program Characterization
TACO 12
(pdf)
- COMPASS: A Community-driven Parallelization Advisor for Sequential Software
IWMSE 09
(pdf)
Traditional Architecture and Microarchitecture
- Multitasking Workload Scheduling in Flexible-Core Chip Multiprocessors
PACT 2008 (pdf)
- Composable Lightweight Processors
Micro 07
(pdf)
- Distributed TRIPS Microarchitecture
Micro 06
(pdf)
- TRIPS Primary Memory System Design
ICCD 06
(pdf
- Bloom Filters for LSQ and Memory Disambiguation
Micro 03 IEEE Micro Top Picks Selection
(pdf)
- Late Binding Load Store Queues
ISCA 07
(pdf)
- Distributed Selective Re-Execution
ASPLOS 04
(pdf)
Miscellaneous (Concept papers, Wild and Crazy)
- Cat-warmer from microprocessor waste heat - Wild and Crazy Ideas, ASPLOS 2006. (pdf) (ppt)
- I, Robot, Architect - Wild and Crazy Ideas, ASPLOS 2009. (pdf) with John Demme
- Software Defined Roads, ASPLOS 2018. (pdf) with Miguel Arroyo
-
The SPARCHS Project: Hardware Support for Software Security
SysSEC 2011
(pdf)
-
Hardware Enforced Statistical Privacy
Computer Architecture Letters 2016 , Best of CAL 2016
(pdf )
Recruiting
If you are an exceptional student and interested in doing cutting-edge
research in Computer Security, Computer Architecture and Digital
VLSI Design and Security, I invite you to
apply
to join our group. We welcome people of any gender identity or
expression, race, ethnicity, nationality, sexual orientation,
religion, culture, subculture, and political opinion.
(Partially reproduced from Dreamwidth)
.
PhD Students
Research Alumni
PhD:
- Dr. John Demme
Thesis: Overcoming the Intuition Wall: Measurement and Analysis in Computer Architecture
- Dr. Adam Waksman
Thesis: Producing Trustworthy Hardware Using Untrusted Components, Personnel and Resources
- Dr. Mike Su
Thesis: Uncovering Features in Behaviorally Similar Programs
- Dr. Adrian Tang
Thesis: Security Engineering of Hardware-Software Interfaces
- Dr. Yipeng Huang
Thesis: Hybrid
Analog-Digital Co-processing for Scientific Computation
- Dr. Kanad Sinha
Thesis: Repurposing Software Defenses with Specialized Hardware
- Dr. Miguel Arroyo
Thesis: Bespoke
Security for Resource Constrained Cyber-Physical Systems
- Dr. Mohamed Tarek Ibn Ziad
Thesis: Hardware-Software Co-design for Practical Memory Safety
Post-Docs/Research Scientists:
- Jon Weisz (Startup)
- Prof. Chester Rebeiro (IIT-Madras)
- Prof. Joel Porquet (University of California, Davis)
- Prof. Hiroshi Sasaki (Tokyo Tech)
MS Research Students:
- MAJ Julianna Eum (First Employment: Instructor, US Military Academy, West Point)
- Matthew Maycock
- Robert Martin (First Employment: Google)
Teaching
Teaching Times for Fall 19:
- Monday, Wednesday: 10:10 - 11:25, CSEE 4824 Computer Architecture,
Hamilton 717.
Courses
- CSEE 4824: Computer Architecture (Spring 14, Spring 15, Spring 16,
Spring 18, Fall 18, Fall 19, Fall 20)
- COMS 6424: Hardware Security (Fall 18, Spring 21)
- CSEE 6824: Parallel Computer Architecture (Fall 08, Spring 09, Spring 10, Spring 11, Spring 12, Spring 13)
- COMS 4121: Computer Systems for Data Sciences (Spring 15)
- EECS 4340: Computer Hardware Design (Fall 09, Fall 10, Fall 11, Fall 12, Fall 13, Fall 14)
- CSEE 3827: Fundamentals of Computer Systems (Spring 08, Spring 20)
Select Recent Professional Activities
Editorial:
- Associate Editor for IEEE Computer Architecture Letters 2016 - 2020
- Guest Editor, June 2014, IEEE Journal on Emerging and Selected Topics
- Guest Editor, May 2019, IEEE Micro Magazine, Special Issue on Security.
Program Committees:
- ISCA (2021, 2019, 2018, 2017, 2016, 2015, 2014, 2013)
- IEEE Security and Privacy (2021, 2020, 2018, 2017, 2016, 2013, 2012);
- MICRO (2014, 2013);
- Top Picks (2017, 2014, 2013);
- RAID (2014, 2013);
- Usenix Security 2014;
- CCS 2013;
- CGO 2013;
- ISPASS 2012;
- ASPLOS 2010;
- IPDPS 2010
External Review Committees:
- ASPLOS 2013
- HPCA 2014, HPCA 2013
- HiPEAC 2014, HiPEAC 2012
- Also reviewer for several journal papers
Conference Organization:
- Publicity chair for ISCA 2009
- Registration chair for HPCA 2011
- Local arrangements chair for e-Energy 2011
- Co-organized Embedded Systems Chanllege with NYU-Poly 2013
Contact Information
Office: 465 CSB
Directions
Phone:1 212 939 7062
Fax:1 212 666 0140
Snail mail:
Prof. Sethumadhavan
Department of Computer Science
Columbia University
1214 Amsterdam Ave.
450 CSB
Mail Code 0401
New York NY 10027.