On July 2022, I joined the Fermi National Accelerator Laboratory.
I am a hardware engineer and researcher with 10+ years of experience in system-level design, HLS, and FPGA-based acceleration with a Ph.D. in hardware verification. At Columbia University, I was a Research Scientist and member of the System-Level Design Group in the Department of Computer Science.
You can contact me by
- Email: gdg ‹at› fnal ‹dot› gov
Highlights
I am an active contributor to the open-source SoC design and ML acceleration communities:
- hls4ml, a package for machine learning inference in FPGAs (and ASIC), GitHub, Documentation
- ESP, a platform for heterogeneous SoC design and prototype, GitHub, Documentation