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IWLS general information

Area, timing, power optimization	Logic synthesis systems	CMOS, ECL, GaAs optimization
Designer experiences with synthesis	Interface specification and synthesis	Digital noise and EMI
Two-Level logic optimization	Interaction with physical design	Multi-Level logic optimization
Incremental synthesis	FSM optimization and encoding	Asynchronous logic synthesis
Sequential circuit optimization	Pass Transistor Logic	Reachability and coverage analysis
Retiming and resynthesis	Optimization at the RTL level	Technology mapping
Timing verification	FPGA and PLD synthesis	Testing and synthesis for test
Interaction with module generators	Reconfigurable computing	SAT Algorithms and applications

The main goal of IWLS is to foster presentation of new ideas and work in early stages of development. For this reason, the program is very open, with high acceptance rate, heavy use of posters and short 15 min. talks for presentation, and large amounts of time in the schedule for discussions around posters. Focus group discussions are also used to encourage exchange of ideas among all the participants on ``hot'', new and controversial topics.

The accepted papers will be printed in the workshop notes which are distributed to IWLS attendants only.

Authors may submit extended abstracts for their proposed presentation. These must be no less than 1000 words and no greater than 2500 words (5 pages). These abstracts are not intended to be complete papers, but rather should contain the idea of the proposed presentation. We encourage submissions in the early stages of research which may highlight important new problems without necessarily providing complete solutions. The abstracts should be submitted through the electronic submission form.

Important Dates

Submission of papers

IWLS information web site: www.iwls.org

Organizing Committee

Technical Program Committee