``Design, Implementation, and Validation of a New Class of Interface Circuits for Latency-Insensitive Design''
Cheng-Hong Li ,
Rebecca L. Collins,
Sampada Sonalkar, and
Luca P. Carloni.
Appearing in The International Conference for Methods and Models for Codesign (MEMOCODE) , Nice, France 2007.
Abstract
With the arrival of nanometer technologies wire
delays are no longer negligible with respect to gate delays, and
timing-closure becomes a major challenge to System-on-Chip
designers. Latency-insensitive design (LID) has been proposed
as a "correct-by-construction" design methodology to cope with
this problem. In this paper we present the design and implementation
of a new class of interface circuits to support LID
that offers substantial performance improvements with limited
area overhead with respect to previous designs proposed in the
literature. This claim is supported by the experimental results
that we obtained completing semi-custom implementations of the
three designs with a 90nm industrial standard-cell library. We
also report on the formal verification of our design: using the
NuSMV model checker we verified that the RTL synthesizable
implementations of our LID interface circuits (relay stations
and shells) are correct refinements of the corresponding abstract
specifications according to the theory of LID.