Academics
Research
Overview
My research is focused on hardware generation starting from high - level
languages.
One could expect that the tremendous advance in silicon technology would
have imposed appropiate design tools for large systems. The reality is different:
Verilog and VHDL (both of them being essentialy netlist languages) are still
the "de facto" way of designing hardware. We can take advantage of the circuit
modularity (which allows us to build high - level structures, even function
specific black box modules). But the result of combining these modules with
the user code is a huge netlist. So techmaping, optimization and simulation
/ verification are still done at netlist level.
To be cynical, I'll say that most design time consists in finding the various
tools hidden features / bugs, writting many HDL wrappers ( carefully renaming
signals ) and manually verifiying that the tool acctually generated the
desired circuit. The user code (ussualy small) can be designed / verified
with the classical methods, but the result after placing it in the big design
is almost unpredictible. The situation, though hopeless for a theoretician,
is not a real barrier for an experienced engineer: a series of pseudo - random
experiments is run, and the best design (i.e. the first which seems to work)
is kept.
CEC : Columbia Esterel Compiler
The synchronous language Esterel (see www.esterel-technologies.com)
can be translated both into hardware and software. The targets are systems
where a PERFECTLY corect timing operation is required ( s.a. real-time systems,
synch. digital logic, etc.). I am aware that "perfectly correct" is a nonsense,
but "almost correct" also is. We are so used with the later so I had to be
more specific ...
For the h/w engineer, Esterel is a good choice of describing controllers
(i.e. complicated systems involving interconnected state machines; a bus
arbitration mechanism is an intuitive sample ).
Briefly, the high level description allows a more concise design; the high
level semantics allows more powerfull methods for verification; all these
lead to a shorter development time and to a more robust design. Performance
is a delicate issue in compilers / CAD tools: an experienced engineer can
do it better "by hand";
I am now working ( under the guidance of my advisor, prof. Stephen A. Edwards ) to
a hardware syntetiser from Esterel, which is a part of CEC (Columbia Esterel
Compiler). The current version (which includes a h/w synthesiser and a s/w
compiler ) can be downloaded at : landc.cs.columbia.edu/projects.html
My wife - Fenchurch
She is charming, has a powerfull Xilinx XC2V2000 FPGA, 10MB ZBT RAM, a
lot of video / audio input / output codecs, 100BASE-TX Ethernet, flash memory
interface, PS/2 keyboard & mouse ports ... You can see her specs here
.
She is my wife because I love her so much and because my department makes
desperate efforts to turn us into normal people (so I need a wife, isn't
it ? )
Courses, comps and projects
Note:
comp : the comprehensive exam was taken, i.e. the course was not
attended
proj : a project was done for the class; you can visit the link