VHDL, Verilog - STUPID OR WHAT ?

Yes, you're right, they are stupid. Period.
Why use them ? Because there is not something better.

First, there is nothing deep in VHDL. See VHDL as collection of tricks.
Do not try to learn VHDL as a purpose, and do not be proud if you gain VHDL fluency.
Any hacker will laught - it's the same as a writer being proud of knowing a lot of MS Word shortcuts.
On the other hand, these tricks can make your life easier - that's all.

Be proud if you can design the fastest circuit.

You do not write code, but you draw circuits.

The only difference is that you type text instead of using the mouse.


For example,

process(clk, rst)
begin
  if rst='1' then q <= '0'; elsif
    if clk'event and clk='1' then q <= d;
  end if;
end process

This is a f-f w/ asynch. reset. Take it as a building brick.
If you're familiar to schematic capture tools, imagine going to libraries/flip-flops, picking "FDC"
and placing it on the worksheet.

Write it ( and the other 4-5 types of common f-f) on a paper and try to memorize the templates.
Do the same for shift regs, muxes, decoders, etc.
Nasty ? Yes. But, after a while, you'll be able to quickly build more complicated mixed structures,
 w/o loosing the control of your design.

Design original circuits, but do not write "original" VHDL

DO NOT DO NOT DO NOT try to write VHDL by inventing "original" patterns from scratch.
You may be tempted to do so because:
- it's original
- the text is shorter, so cooler
- you're dreaming that you are writing C code - wake up

EVEN IF IT WORKS IT DOESN'T MEAN THAT IT WORKS
BRIEFLY, YOU'RE LOOSING CONTROL
- the resulting circuit may be far from what you want
- the design simulates properly but the circuit works differently
- the circuit may be behave differently when synth. with different tools / versions
- nobody can understand it; this will most likely include (and limit to) yrself
- BUGS in CAD tools are VERY COMMON. There are huge patches due to customer bug reports.
Let other people go crazy instead of you, they are well paid for doing that.

The coolest FPGA design

- WORKS. this means "WORKS" not "my homework seems to work".
As I can't check the former but only the later, the real coolness of your code will remain a secret known only by God.
A good reason to design correct circuits :-)
- has the smallest delay (i.e. can work at the highest clock)
- does not waste area