NC | Publications

A Dynamic and Distributed TDM Slot-Scheduling Protocol for QoS-Oriented Networks-on-Chips.
by Nicola Concer, Andrea Vesco, Riccardo Scopigno and Luca P. Carloni.
In the Proceedings of the International Conference on Computer Design (ICCD), 2011, 162-169. [BibTeX entry]

The Connection-then-Credit Flow Control Protocol for Heterogeneous Multi-Core Systems-on-Chip.
by Nicola Concer, Luciano Bononi, Michael Soulie, Riccardo Locatelli and Luca P. Carloni.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 6, 869-882, Jun. 2010. [BibTeX entry]

Virtual Channels vs. Multiple Physical Networks: A Comparative Analysis.
by Young-Jin Yoon, Nicola Concer, Michele Petracca and Luca P. Carloni.
In the Proceedings of the Design Automation Conference (DAC), 2010, 162-165. [BibTeX entry]

System-Level Tools for NoC-Based Multicore Design.
by Luciano Bononi, Nicola Concer and Miltos Grammatikakis.
in Multicore Embedded Systems, G. Kornaros, Ed. CRC Press, 2010. [BibTeX entry]

CTC: An End-To-End Flow Control Protocol for Multi-Core Systems-on-Chip.
by Nicola Concer, Luciano Bononi, Michael Soulie, Riccardo Locatelli and Luca P. Carloni.
In the Proceedings of the Third International Symposium on Networks-on-Chip (NOCS), 2009, 193-202. [BibTeX entry]

aEqualized: a Novel Routing Algorithm For The Spidergon Network On Chip.
by Nicola Concer, Salvatore Iamundo and Luciano Bononi.
In the Proceedings of the Conference on Design, Automation and Test in Europe (DATE), 2009. [BibTeX entry]

Distributed Flit-Buffer Flow Control for Networks-on-Chip.
by Nicola Concer, Michele Petracca and Luca P. Carloni.
In the Proceedings of the 6th International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2008, 215-220. [BibTeX entry]

NoC Topologies Exploration based on Mapping and Simulation Models.
by Luciano Bononi, Nicola Concer and Miltos Grammatikakis.
In the The Proceedings of the 10th Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD) , 2007. [BibTeX entry]

Simulation and Analysis of Network on Chip Architectures: Ring, Spidergon and 2D Mesh.
by Nicola Concer, Salvatore Iamundo and Luciano Bononi.
In the Proceedings of the Conference on Design, Automation and Test in Europe (DATE), 2006. [BibTeX entry]