Handout #1 |
Course Information ( PDF ) |
Handout #2 |
Syllabus ( PDF ) |
Handout #3 |
Homework, Project and Exam Schedule ( PDF ) |
Handout #4 |
Questionnaire ( PDF ) |
Handout #5 |
The Quine-McCluskey Method ( PDF ) |
Lecture #1: Slides ( PDF ) |
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Handout #6 |
Multi-Output Functions (hardcopy only)* |
Handout #7 |
Heuristic Minimization of Two-Level Circuits (hardcopy only)* |
Handout #8 |
Rick Rudell's PhD Thesis: Chapters 1 and 2 ( PDF ) |
Lecture #2 (part 1): Slides ( PDF ) |
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Lecture #2 (part 2): Slides ( PDF ) |
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Handout #9 |
Homework #1 (PDF ) |
Handout #9a |
Homework #1, Problem #1 (TXT ) (Getting Started with SIS ) |
Handout #10 |
Heuristic Two-Level Logic Minimization (hardcopy only)* |
Handout #11 |
Overview of Tautology Checking (PDF ) |
Handout #12 |
Handout of Examples (PDF ) |
Lecture #3: Slides ( PDF ) |
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Handout #13 |
Homework #2 (PDF ) |
Handout #14 |
Selected Problems (ch. 5.8) (hardcopy only)* |
Handout #15 |
Overview of Fast Complementation (PDF ) |
Handout #16 |
Rudell's Master's thesis (UC Berkeley): chs. 4.7-4.8 Last-gasp, super-gasp, make-sparse (PDF ) |
Handout #17 |
Overview of Fast Prime Generation (PDF ) |
Handout #18 |
Prime Generation Problem Example (PDF ) |
Handout #19 |
Homework #3 (PDF ) |
Lecture #5: Slides ( PDF ) |
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Handout #20 |
Kernels, Co-Kernels and Extraction Examples (PDF ) |
Handout #21 |
Homework #1 Solutions (hardcopy only)* |
Handout #22 |
Homework #2 Solutions (hardcopy only)* |
Lecture #6: Slides ( PDF ) |
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Handout #23, #23(a-e) |
#23 Midterm Homework and CAD Project ( PDF ) #23a Midterm CAD Project: Designing a Multi-Cube Extraction Tool ( TXT ) #23b Introduction to the SIS CAD Package: Multi-Level Logic Optimization ( TXT ) #23c Midterm CAD Project: Sample Multi-Cube Extraction Benchmark and Format ( TXT ) #23d Midterm CAD Project: Writeup, Submission and Demo Information ( TXT )#23e Midterm CAD Project: Frequently-Asked Questions (FAQ) *(Updated Regularly -- Refresh Your Browser)* ( TXT ) |
Handout #24 |
Basic Tree-Based Covering Example (area-oriented) (PDF ) |
Handout #25 |
Homework #3 Solutions (hardcopy only)* |
Handout #26 |
Delay-Oriented Technology Mapping Handout (PDF ) |
Handout #27 |
"Technology Mapping for Low Power," V. Tiwari, P. Ashar and S. Malik, Proceedings of ACM/IEEE Design Automation Conference (1993) (PDF ) |
Handout #27a |
Errata and Clarifications: Tiwari et al. paper (#27) (TXT ) |
Handout #28 |
Homework #4 (PDF ) |
Handout #29 |
"A Procedure for Placement of Standard-Cell VLSI Circuits", A.E. Dunlop and B.W. Kernighan, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (Jan. 1985) (PDF ) |
Handout #30 |
Partitioning Overview (courtesy of Prof. David Pan, UT Austin) (PDF ) |
Handout #31 |
Kernighan-Lin Partitioning Example (courtesy of Prof. David Pan, UT Austin) (PDF ) |
Handout #32 |
Midterm CAD Problem (written, SIS) Solutions (hardcopy only)* |
Handout #33 |
"Retiming Synchronous Circuitry," C.E. Leiserson and J.B. Saxe, Algorithmica (1991), 6:5-35 ( PDF) |
Handout #34, #34(a-i) |
#34 Final Homework and CAD Project ( PDF ) #34a Introduction to the SIS CAD Package: Technology Mapping ( TXT ) #34b Final CAD Project: Designing a Retiming Tool ( TXT ) #34c Final CAD Project: Correlator Example ( TXT ) #34d Final CAD Project: Alternative Example: More Complex Correlator ( TXT ) #34e Final CAD Project: Input and Output Format Requirements ( TXT ) #34f Important Clarifications (TXT ) #34g Checkpoint Information ( TXT ) #34h Final Report and Submission Information ( TXT ) #34i Final Demo Information ( TXT )
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Handout #35 |
"An Introduction to High-Level Synthesis," P. Coussy, D.D. Gajski, M. Meredith and A. Takach, IEEE Design and Test of Computers (July/Aug. 2009), pp. 8-17 (PDF ) |
Handout #36 |
"High-Level Synthesis: Past, Present, and Future," G. Martin and G. Smith, IEEE Design and Test of Computers (July/Aug. 2009), pp. 18-24 (PDF ) |
Handout #37 |
Resource Sharing Handout (hardcopy only)* |
Handout #38 |
Scheduling Handout (hardcopy only)* |
Lecture #12: Slides ( PDF ) |
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Handout #39 |
Homework #4 Solutions (hardcopy only)* |
Handout #40 |
Introduction to Asynchronous Design (slides) (PDF ) |
Handout #41 |
Asynchronous Design: Overview Article |
Handout #42 |
Introduction to Hazard-Free Logic Synthesis (PDF ) |
Lecture #14: Slides ( PDF ) |
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Handout #43 |
Introduction to Approximate Computing |
Handout #44 |
Synthesis and Optimization of Digital Microfluidic Biochips (slides) (courtesy of Prof. Krishnendu Chakrabarty, Duke University) (PPT ) |
Handout #45 |
High-Level Synthesis for Digital Microfluidic Biochips |