2016
| [IC.37] | P. Mantovani, E. Cota, C. PILATO, G. Di Guglielmo, L. P. Carloni. “Handling Large Data Sets for High-Performance Embedded Applications in Heterogeneous Systems-on-Chip”, in Proceedings of ACM/IEEE International Conference on Compilers, Architectures, and Synthesis for Embedded Systems (CASES 2016), Pittsburgh, PA, USA, October 2-7, 2016, (to appear). |
| [IC.36] | P. Mantovani, E. Cota, K. Tien, C. PILATO, G. Di Guglielmo, K. Shepard, L. P. Carloni. “An FPGA-Based Infrastructure for Fine-Grained DVFS Analysis in High-Performance Embedded Systems”, in Proceedings of 53rd ACM/IEEE Design Automation Conference (DAC 2016), Austin, TX, USA, June 5-9, 2016, pp. 1-6, (to appear). |
| [WS.11] | G.C. Durelli, F. Spada, R. Cattaneo, C. Pilato, D. Pau, M.D. Santambrogio. “Scala-based Domain-Specific Language for Creating Accelerator-based SoCs”, in Proceedings of 23rd Reconfigurable Architectures Workshop (RAW 2016), Chicago, IL, USA, May 23-24, 2016, (to appear). |
| [WS.10] | C. Pilato, Q. Xu, P. Mantovani, G. Di Guglielmo, L.P. Carloni. “On the Design of Scalable and Reusable Accelerators for Big Data Applications”, in Proceedings of Workshop on Big Data Analytics (BigDAW 2016), Como, Italy, May 16-18, 2016, (to appear). |
2015
| [JR.8] | R. Nane, V.-M. Sima, C. PILATO, J. Choi, B. Fort, A. Canis, Y.T. Chen, H. Hsiao, S. Brown, F. Ferrandi, J. Anderson, K. Bertels. “A Survey and Evaluation of FPGA High-Level Synthesis Tools”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, (to appear). |
| [JR.7] | M. Lattuada, C. PILATO, F. Ferrandi. “Performance Estimation of Task Graphs based on Path Profiling”, in International Journal of Parallel Programming, (to appear). |
2014
| [JR.6] | D. Pnevmatikatos, K. Papadimitriou, T. Becker, P. Bhm, A. Brokalakis, K. Bruneel, C. Ciobanu, T. Davidson, G. Gaydadjiev, K. Heyse, W. Luk, X. Niu, I. Papaefstathiou, D. Pau, O. Pell, C. PILATO, M.D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman, E. Vansteenkiste. “FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration”, in Microprocessors and Microsystems, pp. 1-18, November 2014. |
| [IC.35] | C. PILATO, P. Mantovani, G. Di Guglielmo, L.P. Carloni. “System-Level Memory Optimization for High-Level Synthesis of Component-Based SoCs”, in Proceedings of ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2014), New Delhi, India, October 12-17, 2014, pp. 1-10. |
| [IC.34] | G. Di Guglielmo, C. PILATO, L.P. Carloni. “A Design Methodology for Compositional High-Level Synthesis of Communication-Centric SoCs”, in Proceedings of 51st ACM/IEEE Design Automation Conference (DAC 2014), San Francisco, CA, USA, June 1-5, 2014, pp. 1-6 |
| [W.6] | P. Mantovani, E.G. Cota, S. Kim, K. Tien, J. Chan, G. Di Guglielmo, C. Pilato, M.A. Kim, M. Seok, K. Shepard, L.P. Carloni. “Benchmarking Methodology for Embedded Scalable Platforms”, in Proceedings of Workshop on Suite of Embedded Applications and Kernels (SEAK 2014) (held in conjunction with DAC 2014), San Francisco, CA, USA, June 1, 2014. (poster presentation). |
| [WS.9] | G.C. Durelli, F. Spada, R. Cattaneo, C. Pilato, D. Pau, M.D. Santambrogio. “Adaptive Raytracing Implementation using Partial Dynamic Reconfiguration”, in Proceedings of 21st Reconfigurable Architectures Workshop (RAW 2014), Phoenix, AZ, USA, May 19-20, 2014. |
| [WS.8] | R. Cattaneo, R. Bellini, G.C. Durelli, C. PILATO, M.D. Santambrogio, D. Sciuto. “PaRA-Sched: a Reconfiguration-Aware Scheduler for Reconfigurable Architectures”, in Proceedings of 21st Reconfigurable Architectures Workshop (RAW 2014), Phoenix, AZ, USA, May 19-20, 2014. |
| [IC.33] | D.N. Pnevmatikatos, T. Becker, A. Brokalakis, G.N. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, D. Pau, O. Pell, C. PILATO, M.D. Santambrogio, D. Sciuto, D. Stroobandt,. “Effective Reconfigurable Design: The FASTER Approach”, in Proceedings of 10th International Symposium on Applied Reconfigurable Computing (ARC 2014), Algarve, Portugal, April 14-16, 2014, pp. 318-323. |
| [IC.32] | A.A. Nacci, G. Bettinazzi, C. PILATO, V. Rana, M.D. Santambrogio, D. Sciuto. “A SystemC-Based Framework for the Simulation of Appliances Networks in Energy-Aware Smart Spaces”, in Proceedings of IEEE World Forum on Internet of Things (WF-IoT 2014), Seoul, South Korea, March 6-8, 2014. |
2013
| [IC.31] | R. Cattaneo, C. PILATO, G. Durelli, M.D. Santambrogio, D. Sciuto. “SMASH: A Heuristic Methodology for Designing Partially Reconfigurable MPSoCs”, in Proceedings of IEEE International Symposium on Rapid System Prototyping (RSP 2013), Montreal, Canada, October 3-4, 2013, pp. 102-108. |
| [W.5] | A.A. Nacci, C. PILATO, M.D. Santambrogio, D. Sciuto. “Designing Self-Adaptive Smart Spaces for Energy Saving”, in Proceedings of 2nd Workshop on Self-Awareness in Reconfigurable Computing Systems (SRCS 2013), Porto, Portugal, September, 5, 2013, pp. 1-4. |
| [IC.30] | C. PILATO, F. Ferrandi. “Bambu: A Modular Framework for the High Level Synthesis of Memory-Intensive Applications”, in Proceedings of 23rd International Conference on Field Programmable Logic and Applications (FPL 2013), Porto, Portugal, September 2-4, 2013, pp. 1-4. |
| [IC.29] | C. Ciobanu, G. Gaydadjiev, C. PILATO, D. Sciuto. “Dataflow Computing with Polymorphic Registers”, in Proceedings of the IEEE International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS 2013), Samos, Greece, July 15-18, 2013, pp. 314-321. |
| [WS.7] | F. Cancare, C. PILATO, A. Cazzaniga, D. Sciuto, M.D. Santambrogio. “A Complete Methodology to Implement Self Dynamic Reconfigurable FPGA-Based Systems”, in Proceedings of 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2013), Darmstadt, Germany, July, 10-12, 2013, pp. 1-7. |
| [WS.6] | R. Cattaneo, X. Niu, C. PILATO, T. Becker, W. Luk, M.D. Santambrogio. “A Framework for Effective Exploitation of Partial Reconfiguration in Dataflow Computing”, in Proceedings of 8th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2013), Darmstadt, Germany, July, 10-12, 2013, pp. 1-8. |
| [IC.28] | C. PILATO, R. Cattaneo, G. Durelli, A.A. Nacci, M.D. Santambrogio, D. Sciuto. “A2B: an Integrated Framework for Designing Heterogeneous and Reconfigurable Systems”, in Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2013), Torino, Italy, June 25-27, 2013, pp. 198-203. |
| [IC.27] | R. Cattaneo, C. PILATO, M. Mastinu, O. Kadlcek, O. Pell, M.D. Santambrogio. “Runtime Adaptation on Dataflow HPC Platforms”, in Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2013), Torino, Italy, June 25-27, 2013, pp. 84-91. |
| [IC.26] | F. Ferrandi, P.L. Lanzi C. PILATO, D. Sciuto, A. Tumeo. “Ant Colony Optimization for Mapping, Scheduling and Placing in Reconfigurable Systems”, in Proceedings of the 2013 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2013), Torino, Italy, June 25-27, 2013, pp. 47-54. |
| [JR.5] | A. Miele, C. PILATO, D. Sciuto. “A Simulation-based Framework for the Exploration of Mapping Solutions on Heterogeneous MPSoCs”, in International Journal of Embedded and Real-Time Communication Systems, vol. 4, no. 1, pp. 22-41, April 2013. |
| [IC.25] | D. Sciuto, M.D. Santambrogio, C. PILATO, D. Pnevmatikatos, K. Papadimitriou, D. Stroobandt. “The FASTER Vision for Designing Dynamically Reconfigurable Systems”, in Proceedings of the International Conference on IC Design and Technology (ICICDT 2013), Pavia, Italy, May 29-31, 2013, pp. 5-8 (invited paper). |
| [WS.5] | G. Durelli, A. A. Nacci, R. Cattaneo, C. PILATO, D. Sciuto, M.D. Santambrogio. “A Flexible and Reconfigurable Interconnection Structure for FPGA Dataflow Applications”, in Proceedings of 20th Reconfigurable Architectures Workshop (RAW 2013), Boston, MA, USA, May 20-21, 2013. |
| [W.4] | C. PILATO, R. Cattaneo, G. Durelli, A. Nacci, M.D. Santambrogio, D. Sciuto. “A2B: a Framework for the Fast Prototyping of Reconfigurable Systems”, in Proceedings of 7th HiPEAC Workshop on “Reconfigurable Computing” (WRC 2013), Berlin, Germany, January 21, 2013, pp. 1-10. |
2012
| [IC.24] | K. Papadimitriou, C. PILATO, D. Pnevmatikatos, M.D. Santambrogio, C. Ciobanu, T. Todman, T. Becker, T. Davidson, X. Niu, G. Gaydadjiev, W. Luk, D. Stroobandt. “Novel Design Methods and a Tool Flow for Unleashing Dynamic Reconfiguration”, . CSE 2012: 391-398. in Proceedings of 15th IEEE International Conference on Computational Science and Engineering (CSE 2012), Paphos, Cyprus, December 5-7, 2012, pp. 391-398. |
| [IC.23] | A. Miele, C. PILATO, D. Sciuto. “An Automated Framework for the Simulation of Mapping Solutions on Heterogeneous MPSoCs”, in Proceedings of IEEE International Symposium on System-on-Chip (SoC 2012), Tampere, Finland, October 11-12, 2012, pp. 1-6. |
| [IC.22] | D. Pnevmatikatos, T. Becker, A. Brokalakis, K. Bruneel, G. Gaydadjiev, W. Luk, K. Papadimitriou, I. Papaefstathiou, O. Pell, C. PILATO, M. Robart, M.D. Santambrogio, D. Sciuto, D. Stroobandt, T. Todman. “FASTER: Facilitating Analysis and Synthesis Technologies for Effective Reconfiguration”, in Proceedings of 15th Euromicro Conference on Digital System Design (DSD 2012), Cesme, Izmir, Turkey, September 5-8, 2012, pp. 234-241. |
| [IC.21] | A. Cazzaniga, G. Durelli, C. PILATO, D. Sciuto and M.D. Santambrogio. “On the Development of a Runtime Reconfigurable Multicore System-on-Chip”, in Proceedings of 15th Euromicro Conference on Digital System Design (DSD 2012), Cesme, Izmir, Turkey, September 5-8, 2012, pp. 132-135. |
| [IC.20] | A. Bonetto, A. Cazzaniga, G. Durelli, C. PILATO, D. Sciuto, M.D. Santambrogio. “An open-source design and validation platform for reconfigurable systems”, in Proceedings of 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway, August 29-31, 2012, pp. 707-710. |
| [IC.19] | C. PILATO, A. Cazzaniga, G. Durelli, A. Otero, D. Sciuto, M.D. Santambrogio. “On The Automatic Integration of Hardware Accelerators into FPGA-based Embedded Systems”, in Proceedings of 22nd International Conference on Field Programmable Logic and Applications (FPL 2012), Oslo, Norway, August 29-31, 2012, pp. 607-610. |
| [IC.18] | A. Bonetto, A. Cazzaniga, G.C. Durelli, C. PILATO, D. Sciuto, M.D. Santambrogio. “TaBit: a Framework for Task Graph to Bitstream Generation”, in Proceedings of IEEE International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS 2012), Samos, Greece, July 16-19, 2012, pp. 1-8. |
| [WS.4] | M.D. Santambrogio, D. Pnevmatikatos, K. Papadimitriou, C. PILATO, G. Gaydadjiev, D. Stroobandt, T. Davidson, T. Becker, T. Todman, W. Luk, A. Bonetto, A. Cazzaniga, G. Durelli, D. Sciuto. “Smart Technologies for Effective Reconfiguration: The FASTER approach”, in Proceedings of 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2012), York, UK, July, 9-11, 2012, pp. 1-7. |
| [WS.3] | G. Durelli, A. Cazzaniga, C. PILATO, M.D. Santambrogio, D. Sciuto. “Automatic Run-Time Manager Generation for Reconfigurable MPSoC Architectures”, in Proceedings of 7th International Workshop on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC 2012), York, UK, July, 9-11, 2012, pp. 1-8. |
2011
| [JR.4] | S. Cecchi, A. Primavera, F. Piazza, F. Bettarelli, E. Ciavattini, R. Toppi, J.G.F. Coutinho, W. Luk, C. PILATO, F. Ferrandi, V.M. Sima, K. Bertels. “The hArtes CarLab: A new approach to advanced algorithms development for automotive audio”, in Journal of the Audio Engineering Society, vol. 59, no. 11, pp. 858-869, November 2011. |
| [IB.4] | F. Bettarelli, E. Ciavattini, A. Lattanzi, G. Beltrame, F. Ferrandi, L. Fossati, C. PILATO, D. Sciuto, R.J. Meeuws, S.A. Ostadzadeh, Z. Nawaz, Y. Lu, T. Marconi, M. Sabeghi, V.M. Sima, K. Sigdel. “Extensions of the hArtes Tool Chain”, in “Hardware/Software Co-design for Heterogeneous Multi-core Platforms”, K. Bertels (Ed.), Springer, November 2011, pp. 193-228. |
| [IB.3] | S. Cecchi, L. Palestini, P. Peretti, A. Primavera, F. Piazza, F. Capman, S. Thabuteau, C. Levy, J.F. Bonastre, A. Lattanzi, E. Ciavattini, F. Bettarelli, R. Toppi, E. Capucci, F. Ferrandi, M. Lattuada, C. PILATO, D. Sciuto, W. Luk, J.G.F. Coutinho. “In Car Audio”, in “Hardware/Software Co-design for Heterogeneous Multi-core Platforms”, K. Bertels (Ed.), Springer, November 2011, pp. 155-192. |
| [IB.2] | K. Bertels, A. Lattanzi, E. Ciavattini, F. Bettarelli, M.T. Chiaradia, R. Nutricato, A. Morea, A. Antola, F. Ferrandi, M. Lattuada, C. PILATO, D. Sciuto, R.J. Meeuws, Y. Yankova, V.M. Sima, K. Sigdel, W. Luk, J.G.F. Coutinho, Y.M Lam, T. Todman, A. Michelotti, A. Cerruto. “The hArtes Tool Chain”, in “Hardware/Software Co-design for Heterogeneous Multi-core Platforms”, K. Bertels (Ed.), Springer, November 2011, pp. 9-110. |
| [IC.17] | C. PILATO, F. Ferrandi, D. Sciuto. “A Design Methodology to Implement Memory Accesses in High-Level Synthesis”, in Proceedings of ACM/IEEE International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS 2011), Taipei, Taiwan, October 9-14, 2011, pp. 49-58. |
| [IC.16] | C. PILATO, V.G. Castellana, S. Lovergine, F. Ferrandi. “A Runtime Adaptive Controller for Supporting Hardware Components with Variable Latency”, in Proceedings of 2011 NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2011), San Diego, CA, USA, June 6-9, 2011, pp. 153-160. |
| [IC.15] | C. Bolchini, A. Miele, C. PILATO. “Combined Architecture and Hardening Techniques Exploration for Reliable Embedded System Design”, in Proceedings of 31st ACM Great Lakes Symposium on VLSI (GLSVLSI 2011), Lausanne, Switzerland, May 2-4, 2011, pp. 301-306. |
| [IC.14] | C. PILATO, F. Ferrandi, D. Pandini. “A Design Methodology for the Automatic Sizing of Standard-Cell Libraries”, in Proceedings of 31st ACM Great Lakes Symposium on VLSI (GLSVLSI 2011), Lausanne, Switzerland, May 2-4, 2011, pp. 151-156. |
| [WS.2] | C. PILATO, F. Ferrandi, D. Pandini. “Evaluating Static CMOS Complex Cells in Technology Mapping”, in Proceedings of Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms (ERDIAP 2011), Como, Italy, February, 23, 2011, pp. 222-229. |
| [WS.1] | M. Elhoj, A. Reis, R. Ribas, F. Ferrandi, C. PILATO, F. Moll, M. Miranda, P. Dobrovolny, N. Woolaway, A. Grasset, P. Bonnot, G. Desoli, D. Pandini. “SYNAPTIC Project: Regularity Applied to Enhance Manufacturability and Yield at Several Abstraction Levels”, invited paper, in Proceedings of Workshop on Exploiting Regularity in the Design of IPs, Architectures and Platforms (ERDIAP 2011), Como, Italy, February, 23, 2011, pp. 189-192. |
2010
| [IC.13] | S. Cecchi, A. Primavera, F. Piazza, F. Bettarelli, E. Ciavattini, R. Toppi, J.G.F. Coutinho, W. Luk, C. PILATO, F. Ferrandi, V. M. Sima, K. Bertels. “The hArtes CarLab: A New Approach to Advanced Algorithms Development for Automotive Audio”, in Proceedings of 129th Audio Engineering Society Convention (AES 2010), San Francisco, CA, USA, November 4-7, 2010, pp. 1-12. |
| [JR.3] | K. Bertels, V.M. Sima, Y. Yankova, G. Kuzmanov, W. Luk, J.G.F. Coutinho, F. Ferrandi, C. PILATO, M. Lattuada, D. Sciuto, A. Michelotti. “hArtes: Hardware-Software Codesign for Heterogeneous Multicore Platforms”, in IEEE Micro, vol. 30, no. 5, pp. 88-97, September/October 2010. |
| [IC.12] | C. PILATO, F. Ferrandi, D. Pandini. “A Fast Heuristic for Extending Standard Cell Libraries with Regular Macro Cells”, in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2010), Lixouri, Kefalonia, Greece, July 5-7, 2010, pp. 23-28. |
| [JR.2] | F. Ferrandi, P. L. Lanzi, C. PILATO, D. Sciuto, A. Tumeo. “Ant Colony Heuristic for Mapping and Scheduling Task and Communications on Heterogeneous Embedded Systems”, in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 29, no. 6, pp. 911-924, June 2010. | [W.3] | C. PILATO, F. Ferrandi, D. Sciuto. “A Design Exploration Framework for Mapping and Scheduling onto Heterogeneous MPSoCs”, in 3rd Workshop on “Mapping Applications to MPSoCs”, St. Goar, Germany, June 29-30, 2010. |
| [W.2] | F. Ferrandi, M. Lattuada, C. PILATO, D. Sciuto. “Performance Estimation for Mapping and Scheduling Parallel Applications on Heterogeneous Multi-Processor Systems”, in Workshop on “The European landscape of reconfigurable computing: Lessons learned, new perspectives and innovations”, held during DATE 2010, Dresden, Germany, March 12, 2010. |
| [IB.1] | C. PILATO, D. Loiacono, A. Tumeo, F. Ferrandi, P. L. Lanzi and D. Sciuto. “Speeding-Up Expensive Evaluations in High-Level Synthesis Using Solution Modeling and Fitness Inheritance”, in “Computational Intelligence in Expensive Optimization Problems”, Y. Tenne and C.-K. Goh (Eds.), Springer, February 2010, pp. 701-723. |
| [IC.11] | F. Ferrandi, C. PILATO, A. Tumeo, D. Sciuto. “Mapping and Scheduling of Parallel C Applications with Ant Colony Optimization onto Heterogeneous Reconfigurable MPSoCs”, in Proceedings of IEEE Asia and South Pacific Design Automation Conference (ASPDAC 2010), Taipei, Taiwan, January 18-21, 2010, pp. 799-804. |
2009
| [IC.10] | M. Branca, L. Camerini, F. Ferrandi, P. L. Lanzi, C. PILATO, D. Sciuto, A. Tumeo. “Mapping pipelined applications onto heterogeneous embedded systems: a Bayesian Optimization Algorithm based approach”, in Proceedings of ACM/IEEE International Conference on Hardware-Software Codesign and System Synthesis (CODES+ISSS 2009), Grenoble, France, October 11-16, 2009, pp. 443-452. |
| [IC.9] | F. Ferrandi, M. Lattuada, C. PILATO, A. Tumeo. “Performance Modeling of Parallel Applications on MPSoCs”, in Proceedings of IEEE International Symposium on System-on-Chip (SOC 2009), Tampere, Finland, October 5-7, 2009, pp. 64-67. |
| [IC.8] | F. Ferrandi, M. Lattuada, C. PILATO, A. Tumeo. “Performance Estimation for Task Graphs Combining Sequential Path Profiling and Control Dependence Regions”, in Proceedings of ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), Cambridge, MA, USA, 2009, July 13-15, 2009, pp. 131-140. |
| [IC.7] | M. Branca, L. Camerini, F. Ferrandi, P. L. Lanzi, C. PILATO, D. Sciuto, A. Tumeo. “Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems”, in Proceedings of ACM/IEEE Genetic and Evolutionary Computation Conference (GECCO 2009), Montreal, Canada, July 8-12, 2009, pp. 1435-1442. |
| [IC.6] | A. Tumeo, C. PILATO, G. Palermo, F. Ferrandi, D. Sciuto. “HW/SW methodologies for synchronization in FPGA multiprocessors”, in Proceedings of ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2009), Monterey, CA, USA, February 22-24, 2009, pp. 265-268. |
2008
| [JR.1] | C. PILATO, A. Tumeo, G. Palermo, F. Ferrandi, P. L. Lanzi and D. Sciuto. “Improving Evolutionary Exploration to Area-Time Optimization of FPGA Designs”, in Journal of Systems Architecture, Volume 54, No. 11, pp. 1046-1057, November 2008. |
| [IC.5] | A. Tumeo, C. PILATO, F. Ferrandi, D. Sciuto, P. L. Lanzi. “Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems”, in Proceedings of IEEE International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VIII), Samos, Greece, July 21-24 2008, pp. 142-149. |
| [IC.4] | C. PILATO, D. Loiacono, F. Ferrandi, P. L. Lanzi, D. Sciuto. “High-level Synthesis with Multi-objective Genetic Algorithm: a Comparative Encoding Analysis”, in Proceedings of IEEE Congress on Evolutionary Computation (CEC 2008), Hong Kong (China), June 1-6, 2008, pp. 3334-3341. |
| [IC.3] | C. PILATO, D. Loiacono, F. Ferrandi, P. L. Lanzi, D. Sciuto. “A multi-objective genetic algorithm for design space exploration in high-level synthesis”, in Proceedings of IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2008), Montpellier, France, April 7-9, 2008, pp. 417-422. |
| [W.1] | C. PILATO, F. Ferrandi, P. L. Lanzi G. Palermo, A. Tumeo, D. Sciuto. “Bambu: a High Level Synthesis Framework with Evolutionary Design Space Exploration”, in Workshop on “The New Wave of the High-Level Synthesis”, held during DATE 2008, Munich, Germany, March 14, 2008. |
2007
| [IC.2] | C. PILATO, G. Palermo, A. Tumeo, F. Ferrandi, D. Sciuto and P. L. Lanzi. “Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis”, in Proceedings of IEEE Congress on Evolutionary Computation (CEC 2007), Singapore, September 25-28, 2007, pp. 3459-3466. |
| [IC.1] | F. Ferrandi, P. L. Lanzi, G. Palermo, C. PILATO, D. Sciuto and A. Tumeo. “An Evolutionary Approach to Area-Time Optimization of FPGA designs”, in Proceedings of IEEE International Conference on Embedded Computer Systems: Architectures, MOdeling, and Simulation (SAMOS VII), Samos, Greece, July 16-19, 2007, pp. 145-152. |