Gabriele Tombesi

Computer Science PhD Student

I am a third year PhD student, part of the System-Level Design Group at Columbia University. My Research interests include HLS-based design flows for hardware acceleration of Deep Learning workloads and Design for Testability techniques for heterogeneous system-on-chip architectures. I am currently conducting research on tiled hardware accelerators for deep learning, with a focus on innovative intra-layer parallelism and inter-layer pipelining techniques. 

I received the joint M.S. degree in Electrical Engineering from the Politecnico di Torino, École Polytechnique Fédérale de Lausanne and Grenoble INP and the B.S. degree in Physical Engineering from the Politecnico di Torino.

gtombesi

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Resume

gtombesi@cs.columbia.edu

Education

• Polytechnic of Turin

B.Sc. in Physical Engineering (October 2018)

• Polytechnic of Turin-INP-EPFL 

M.Sc in Electrical Engineering (October 2020)

• Columbia University

Ph.D. in Computer Science (Excpected: Jul 2026)

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Projects

• ESP is an open-source research platform for heterogeneous system-on-chip design developed by the SLD group at Columbia University. It combines a scalable tile-based architecture and a flexible system-level design methodology. The architecture includes a set of platforms services, such as DMA, distributed interrupt, and run-time coherence selection, to facilitate the IP integration into the SoC and  enable rapid full-system prototyping on FPGA. The methodology provides three different accelerator design flows (RTL, high-level synthesis and ML frameworks) based on templates and scripts that accomodate different users needs.

• EPOCHS is a collaboration between IBM, Columbia, Harvard, and UIUC, funded within the DARPA Domain-Specific System-on-Chip (DSSOC) program. EPOCHS is part of an effort to enable the rapid development of multi-application systems through a single programmable device.

• DECADES is a DARPA-funded project led by PIs from Princeton and Columbia to create specialized, reconfigurable hardware to accelerate important applications.

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Publications

SoCProbe: Compositional Post-Silicon Validation of Heterogeneous NoC-Based SoCs.
Gabriele Tombesi, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Maico Cassel Dos Santos, Tianyu Jia, David Brooks, Gu-Yeon Wei, Luca P Carloni.
In IEEE Design & Test 2023 - NOCS’23 Special Issue - Best Paper Award .

A 12nm Agile-Designed SoC for Swarm-Based Perception with Heterogeneous IP Blocks, a Reconfigurable Memory Hierarchy, and an 800MHz Multi-Plane NoC .
Tianyu Jia, Paolo Mantovani, Maico Cassel Dos Santos, Davide Giri,Joseph Zuckerman,Erik Jens Loscalzo, Martin Cochet, Karthik Swaminathan, Gabriele Tombesi, Jeff Jun Zhang, Nandhini Cahndromoorthy, John-David Wellman, Kevin Tien, and Luca P. Carloni
In Proceedings of the European Conference on Solid-State Circuits (ESSCIRC), 2022.

A Scalable Methodology for Agile Chip Development with Open-Source Hardware Components.
Maico Cassel Dos Santos, Tianyu Jia, Martin Cochet, Karthik Swaminathan, Joseph Zuckerman, Paolo Mantovani, Davide Giri, Jeff Jun Zhang, Erik Jens Loscalzo, Gabriele Tombesi, Kevin Tien, Nandhini Chandramoorthy, John-David Wellman, David Brooks, Gu-Yeon Wei, Kenneth Shepard, Luca Carloni, and Pradip Bose.
In Proceedings of the IEEE International Conference on Computer-Aided Design (ICCAD), 2022.

DECADES: A 67mm2, 1.46TOPS, 55 Giga Cache-Coherent 64-bit RISC-V Instructions per second, Heterogeneous Manycore SoC with 109 Tiles including Accelerators, Intelligent Storage, and eFPGA in 12m FinFET.
F. Gao, T.-J. Chand, A. Li, M. Orenes-Vera, D. Giri, P. Jackson, A. Ning, G. Tziantzioulis, Joseph Zuckerman, J. Tu, K. Xu, G. Chirkov, Gabriele Tombesi, J. Balkind, M. Martonosi, L. Carloni, and D. Wentzlaff.
In Proceedings of the Custom Integrated Circuits Conference (CICC), 2023.

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Work Experience

• Columbia University
  Graduate Research Assistant
  January 2021 - Present
  New York City 
  
  
• Columbia University
  Teaching Assistant for
  System-on-Chip Platforms (CSEE W4868)
  September - December 2022
  New York City 
  
  
• Columbia University
  Research Intern 
  March - October 2022
  New York City 
  Design of a Debug Unit which provides a flexible, platform-based pre- and post-silicon verification methodology to address the increasing complexity of modern heterogeneous System-on-Chips (SoCs).
  
  
• IBM 
  Nanofabrication and
  Characterization Intern
  June - August 2019
  San Jose
  Processing of vacuum-deposited metal oxide semiconductors (MOS) films and testing of their electrical and sensing properties, targeting orthogonal response when exposed to specific volatile organic compounds mixtures.
  

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