Publications

2021

Accelerator Integration for Open-Source SoC Design.

Davide Giri, Kuan-Lin Chiu, Guy Eichler, Paolo Mantovani, and Luca P. Carloni.

IEEE Micro (Special Issue: FPGAs in Computing), 2021.

PDF BibT_EX

@article{giri_ieeemicro21,
  author = {Giri, Davide and Chiu, Kuan-Lin and Eichler, Guy and Mantovani, Paolo and Carloni, Luca P.},
  journal = {IEEE Micro (Special Issue: FPGAs in Computing)},
  title = {Accelerator Integration for Open-Source SoC Design},
  year = {2021}
}

2020

Agile SoC Development with Open ESP.

Paolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, and Luca P. Carloni.

In Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2020.

PDF BibT_EX

@inproceedings{mantovani_iccad20,
  author = {Mantovani, Paolo and Giri, Davide and Di Guglielmo, Giuseppe and Piccolboni, Luca and Zuckerman, Joseph and Cota, Emilio G. and Petracca, Michele and Pilato, Christian and Carloni, Luca P.},
  title = {{Agile SoC Development with Open ESP}},
  journal = {Proceedings of the International Conference on Computer-Aided Design (ICCAD)},
  year = {2020},
  month = {October}
}

Ariane + NVDLA: Seamless Third-Party IP Integration with ESP.

Davide Giri, Kuan-Lin Chiu, Guy Eichler, Paolo Mantovani, Nandhini Chandramoorthy, and Luca P. Carloni.

In Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV), 2020.

PDF BibT_EX

@inproceedings{giri_carrv20,
  author = {Giri, Davide and Chiu, Kuan-Lin and Eichler, Guy and Mantovani, Paolo and Chandramoorthy, Nandhini and Carloni, Luca P.},
  title = {{Ariane + NVDLA: Seamless Third-Party IP Integration with ESP}},
  journal = {Proceedings of the Workshop on Computer Architecture Research with RISC-V (CARRV)},
  year = {2020},
  month = {May}
}

HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis.

Paolo Mantovani, Robert Margelli, Davide Giri, and Luca P. Carloni.

In Proceedings of the Custom Integrated Circuits Conference (CICC), 2020.

PDF BibT_EX

@inproceedings{mantovani_cicc20,
  author = {Mantovani, Paolo and Margelli, Robert and Giri, Davide and Carloni, Luca P.},
  title = {{HL5: A 32-bit RISC-V Processor Designed with High-Level Synthesis}},
  journal = {Proceedings of the Custom Integrated Circuits Conference (CICC)},
  year = {2020},
  month = {March}
}

ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning.

Davide Giri, Kuan-lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, and Luca P. Carloni.

In Proceedings of the Conference on Design, Automation and Test in Europe (DATE), 2020.

Best paper nominee PDF BibT_EX

@inproceedings{giri_date20,
  author = {Giri, Davide and Chiu, Kuan-lin and Di Guglielmo, Giuseppe and Mantovani, Paolo and Carloni, Luca P.},
  title = {ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine Learning},
  booktitle = {Proceedings of the Conference on Design, Automation and Test in Europe (DATE)},
  year = {2020},
  month = {March}
}

2019

Teaching Heterogeneous Computing with System-Level Design Methods.

Luca P. Carloni, Emilio G. Cota, Giuseppe Di Guglielmo, Davide Giri, Jihye Kwon, Paolo Mantovani, Luca Piccolboni, and Michele Petracca.

In Proceedings of the Workshop on Computer Architecture Education, 2019, 4:1–4:8.

PDF BibT_EX

@inproceedings{carloni_wcae19,
  author = {Carloni, Luca P. and Cota, Emilio G. and Guglielmo, Giuseppe Di and Giri, Davide and Kwon, Jihye and Mantovani, Paolo and Piccolboni, Luca and Petracca, Michele},
  title = {Teaching Heterogeneous Computing with System-Level Design Methods},
  booktitle = {Proceedings of the Workshop on Computer Architecture Education},
  series = {WCAE'19},
  year = {2019},
  isbn = {978-1-4503-6842-1},
  location = {Phoenix, AZ, USA},
  pages = {4:1--4:8},
  articleno = {4},
  numpages = {8},
  url = {http://doi.acm.org/10.1145/3338698.3338893},
  doi = {10.1145/3338698.3338893},
  acmid = {3338893},
  publisher = {ACM},
  address = {New York, NY, USA}
}

Runtime Reconfigurable Memory Hierarchy in Embedded Scalable Platforms.

Davide Giri, Paolo Mantovani, and Luca P. Carloni.

In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2019.

Invited Paper PDF BibT_EX

@inproceedings{giri_aspdac19,
  author = {Giri, Davide and Mantovani, Paolo and Carloni, Luca P.},
  title = {{Runtime Reconfigurable Memory Hierarchy in Embedded Scalable Platforms}},
  journal = {Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC)},
  year = {2019}
}

2018

Accelerators and Coherence: An SoC Perspective.

Davide Giri, Paolo Mantovani, and Luca P. Carloni.

IEEE Micro (Special Issue: Hardware Acceleration), vol. 38, no. 6, November 2018, 36–45.

PDF BibT_EX

@article{giri_ieeemicro18,
  author = {Giri, Davide and Mantovani, Paolo and Carloni, Luca P.},
  journal = {IEEE Micro (Special Issue: Hardware Acceleration)},
  title = {Accelerators and Coherence: An SoC Perspective},
  year = {2018},
  volume = {38},
  number = {6},
  pages = {36-45},
  month = {November}
}

NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators.

Davide Giri, Paolo Mantovani, and Luca P. Carloni.

In Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2018.

PDF BibT_EX

@inproceedings{giri_nocs18,
  author = {Giri, Davide and Mantovani, Paolo and Carloni, Luca P.},
  title = {{NoC-Based Support of Heterogeneous Cache-Coherence Models for Accelerators}},
  journal = {Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip (NOCS)},
  year = {2018}
}

2017

COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators.

Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni.

ACM Transactions on Embedded Computing Systems, vol. 16, no. 5s, September 2017.

PDF BibT_EX

@article{piccolboni_tecs17,
  author = {Piccolboni, Luca and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.},
  title = {{COSMOS: Coordination of High-Level Synthesis and Memory Optimization for Hardware Accelerators}},
  journal = {ACM Transactions on Embedded Computing Systems},
  volume = {16},
  number = {5s},
  month = {September},
  year = {2017}
}

System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip.

Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni.

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2017.

PDF BibT_EX

@article{pilato_tcad17,
  author = {Pilato, Christian and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.},
  title = {{System-Level Optimization of Accelerator Local Memory for Heterogeneous Systems-on-Chip}},
  journal = {IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year = {2017}
}

Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms.

Luca Piccolboni, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni.

In Proceedings of the IEEE High Performance Extreme Computing Conference (HPEC), 2017.

PDF BibT_EX

@inproceedings{piccolboni_hpec17,
  author = {Piccolboni, Luca and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.},
  booktitle = {{Proceedings of the IEEE High Performance Extreme Computing Conference (HPEC)}},
  title = {{Broadening the Exploration of the Accelerator Design Space in Embedded Scalable Platforms}},
  year = {2017}
}

System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip.

Young Jin Yoon, Paolo Mantovani, and Luca P. Carloni.

In Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 2017.

Invited Paper PDF BibT_EX

@inproceedings{yoon_nocs17,
  author = {Yoon, Young Jin and Mantovani, Paolo and Carloni, Luca P.},
  title = {System-Level Design of Networks-on-Chip for Heterogeneous Systems-on-Chip},
  booktitle = {Proceedings of the Eleventh IEEE/ACM International Symposium on Networks-on-Chip (NOCS)},
  year = {2017}
}

Scalable System-on-Chip Design. Paolo Mantovani. PhD thesis. 2017. PDF BibT_EX

@phdthesis{mantovani_thesis,
  author = {Mantovani, Paolo},
  title = {Scalable System-on-Chip Design},
  journal = {ProQuest Dissertations and Theses},
  pages = {230},
  year = {2017},
  isbn = {9780355042498},
  language = {English},
  url = {http://ezproxy.cul.columbia.edu/login?url=https://search.proquest.com/docview/1925289547?accountid=10226}
}

2016

Handling Large Data Sets for High-Performance Embedded Applications in Heterogeneous Systems-on-Chip.

Paolo Mantovani, Emilio G. Cota, Christian Pilato, Giuseppe Di Guglielmo, and Luca P. Carloni.

In Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES), 2016, 3:1–3:10.

PDF BibT_EX

@inproceedings{mantovani_cases16,
  author = {Mantovani, Paolo and Cota, Emilio G. and Pilato, Christian and Di Guglielmo, Giuseppe and Carloni, Luca P.},
  title = {Handling Large Data Sets for High-Performance Embedded Applications in Heterogeneous Systems-on-Chip},
  booktitle = {Proceedings of the International Conference on Compilers, Architecture and Synthesis for Embedded Systems (CASES)},
  year = {2016},
  month = {October},
  isbn = {978-1-4503-4482-1},
  location = {Pittsburgh, Pennsylvania},
  pages = {3:1--3:10},
  articleno = {3},
  numpages = {10},
  url = {http://doi.acm.org/10.1145/2968455.2968509},
  doi = {10.1145/2968455.2968509},
  acmid = {2968509},
  publisher = {ACM},
  address = {New York, NY, USA}
}

An FPGA-based Infrastructure for Fine-grained DVFS Analysis in High-performance Embedded Systems.

Paolo Mantovani, Emilio G. Cota, Kevin Tien, Christian Pilato, Giuseppe Di Guglielmo, Ken Shepard, and Luca P. Carloni.

In Proceedings of the Design Automation Conference (DAC), 2016, 157:1–157:6.

PDF BibT_EX

@inproceedings{mantovani_dac16,
  author = {Mantovani, Paolo and Cota, Emilio G. and Tien, Kevin and Pilato, Christian and Di Guglielmo, Giuseppe and Shepard, Ken and Carloni, Luca P.},
  title = {An FPGA-based Infrastructure for Fine-grained DVFS Analysis in High-performance Embedded Systems},
  booktitle = {Proceedings of the Design Automation Conference (DAC)},
  year = {2016},
  month = {June},
  pages = {157:1-157:6}
}

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration.

Emilio G. Cota, Paolo Mantovani, and Luca P. Carloni.

In Proceedings of the International Conference on Supercomputing (ICS), 2016, 27:1–27:12.

PDF BibT_EX

@inproceedings{cota_ics16,
  author = {Cota, Emilio G. and Mantovani, Paolo and Carloni, Luca P.},
  title = {Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration},
  booktitle = {Proceedings of the International Conference on Supercomputing (ICS)},
  year = {2016},
  month = {June},
  pages = {27:1-27:12}
}

High-Level Synthesis of Accelerators in Embedded Scalable Platforms.

Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni.

In Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC), 2016, 204–211.

Invited Paper PDF BibT_EX

@inproceedings{mantovani_aspdac16,
  author = {Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.},
  title = {{High-Level Synthesis of Accelerators in Embedded Scalable Platforms}},
  booktitle = {Proceedings of the Asia and South Pacific Design Automation Conference (ASPDAC)},
  pages = {204-211},
  year = {2016},
  month = {January}
}

On the Design of Scalable and Reusable Accelerators for Big Data Applications.

Christian Pilato, Qirui Xu, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni.

In Proceedings of the International Conference on Computing Frontiers (CF), 2016, 406–411.

Invited Paper PDF BibT_EX

@inproceedings{pilato_cf16,
  author = {Pilato, Christian and Xu, Qirui and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.},
  title = {On the Design of Scalable and Reusable Accelerators for Big Data Applications},
  booktitle = {Proceedings of the International Conference on Computing Frontiers (CF)},
  year = {2016},
  pages = {406-411}
}

2015

An Analysis of Accelerator Coupling in Heterogeneous Architectures.

Emilio G. Cota, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni.

In Proceedings of the Design Automation Conference (DAC), 2015, 202:1–202:6.

PDF BibT_EX

@inproceedings{cota_dac15,
  author = {Cota, Emilio G. and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.},
  title = {An Analysis of Accelerator Coupling in Heterogeneous Architectures},
  booktitle = {Proceedings of the Design Automation Conference (DAC)},
  series = {DAC'15},
  year = {2015},
  month = {June},
  isbn = {978-1-4503-3520-1},
  location = {San Francisco, California},
  pages = {202:1--202:6},
  articleno = {202},
  numpages = {6},
  url = {http://doi.acm.org/10.1145/2744769.2744794},
  doi = {10.1145/2744769.2744794},
  acmid = {2744794},
  publisher = {ACM},
  address = {New York, NY, USA}
}

A synchronous latency-insensitive {RISC} for better than worst-case design .

Mario R. Casu and Paolo Mantovani.

Integration, the {VLSI} Journal , vol. 48, no. 0, 2015, 72–82.

BibT_EX

@article{casu_integration15j,
  title = {A synchronous latency-insensitive \{RISC\} for better than worst-case design },
  journal = {Integration, the \{VLSI\} Journal },
  volume = {48},
  number = {0},
  pages = {72 - 82},
  year = {2015},
  issn = {0167-9260},
  doi = {http://dx.doi.org/10.1016/j.vlsi.2014.01.003},
  url = {http://www.sciencedirect.com/science/article/pii/S0167926014000091},
  author = {Casu, Mario R. and Mantovani, Paolo}
}

2014

System-level memory optimization for high-level synthesis of component-based SoCs.

Christian Pilato, Paolo Mantovani, Giuseppe Di Guglielmo, and Luca P. Carloni.

In Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), 2014, 1–10.

PDF BibT_EX

@inproceedings{pilato_codesisss2014,
  author = {Pilato, Christian and Mantovani, Paolo and Di Guglielmo, Giuseppe and Carloni, Luca P.},
  title = {{System-level memory optimization for high-level synthesis of component-based SoCs}},
  booktitle = {Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)},
  year = {2014},
  month = {October},
  pages = {1-10}
}

Accelerator Memory Reuse in the Dark Silicon Era.

Emilio G. Cota, Paolo Mantovani, Michele Petracca, Mario R. Casu, and Luca P. Carloni.

Computer Architecture Letters, vol. 13, no. 1, January 2014, 9–12.

PDF BibT_EX

@article{cota_cal14,
  author = {Cota, Emilio G. and Mantovani, Paolo and Petracca, Michele and Casu, Mario R. and Carloni, Luca P.},
  journal = {Computer Architecture Letters},
  title = {Accelerator Memory Reuse in the Dark Silicon Era},
  year = {2014},
  month = {January},
  volume = {13},
  number = {1},
  pages = {9-12},
  doi = {10.1109/L-CA.2012.29},
  issn = {1556-6056}
}

2012

A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI.

N. Sturcken, Michele Petracca, S. Warren, Paolo Mantovani, Luca P. Carloni, A.V. Peterchev, and Kenneth L. Shepard.

IEEE Journal of Solid-State Circuits, vol. 47, no. 8, August 2012, 1935–1945.

PDF BibT_EX

@article{sturcken_jssc12,
  author = {Sturcken, N. and Petracca, Michele and Warren, S. and Mantovani, Paolo and Carloni, Luca P. and Peterchev, A.V. and Shepard, Kenneth L.},
  title = {{A Switched-Inductor Integrated Voltage Regulator With Nonlinear Feedback and Network-on-Chip Load in 45 nm SOI}},
  journal = {IEEE Journal of Solid-State Circuits},
  year = {2012},
  month = {August},
  volume = {47},
  number = {8},
  pages = {1935-1945}
}

2011

Coupling Latency-insensitivity with Variable-latency for Better Than Worst Case Design: A RISC Case Study.

Mario R. Casu, Stefano Colazzo, and Paolo Mantovani.

In Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI, 2011, 163–168.

PDF BibT_EX

@inproceedings{casu_glsvlsi11,
  author = {Casu, Mario R. and Colazzo, Stefano and Mantovani, Paolo},
  title = {Coupling Latency-insensitivity with Variable-latency for Better Than Worst Case Design: A RISC Case Study},
  booktitle = {Proceedings of the 21st Edition of the Great Lakes Symposium on Great Lakes Symposium on VLSI},
  series = {GLSVLSI '11},
  year = {2011},
  isbn = {978-1-4503-0667-6},
  location = {Lausanne, Switzerland},
  pages = {163--168},
  numpages = {6},
  url = {http://doi.acm.org/10.1145/1973009.1973043},
  doi = {10.1145/1973009.1973043},
  acmid = {1973043},
  publisher = {ACM},
  address = {New York, NY, USA}
}